1. Field of the Invention
This invention relates to a memory cell, and more particularly, a memory cell that can operate under low voltage conditions.
2. Description of the Prior Art
Non-volatile memory (NVM) is a type of memory that retains information it stores even when no power is supplied to memory blocks. FIG. 1 shows a memory array 100 according to prior art. The memory array 100 includes a plurality of memory cells 110A, 110B, and 110C disposed in rows and columns. Each memory cell 110A, 110B, and 110C comprises a transistor 112 and an antifuse transistor 114. Memory cells 110A and 110B disposed in the same row (within same word) receive the same word line selection signal WS1, program control signal PC1 and program data signal PD1 but different bit line selection signals BS1 and BS2. Memory cells 110A and 110C disposed in the same column receive the same bit line selection signal BS1 but different word line selection signals WS1 and WS2, program control signals PC1 and PC2, and program data signals PD1 and PD2.
During the programming operation of the memory cell 110A, the antifuse transistor 114 of the memory cell 110A is ruptured and functions as a MOS capacitor, such that data of logic “1” is written into the memory cell 110A. During the reading operation of the memory cell 110A, the corresponding word line selection signal WS1 received by the memory cell 110A is at a high voltage and the corresponding bit line selection signal BS1 received by the memory cell 110A is at a low voltage so the transistor 112 of the memory cell 110A can be turned on accordingly. Thus, the transistor 112 of the memory cell 110A can form a read current according to the data stored in the antifuse transistor 114 of the memory cell 110A. And the system then can determine the data by the amount of the read current.
However, since the second terminal of the transistor 112 of the memory cells disposed in the same column, such as memory cells 110A and 110C, are coupled together, the read current must charge the parasitic capacitors of all the other memory cells along the column directly. Since the read current formed by the antifuse transistor 114 may be rather small, the long charging path along the column may cause significant decay, increasing the time for reading data from the memory cell 110A. This situation may get even worse when the memory cell is operated with low voltage.